
derive_clocks

create_clock -period 20.000 -waveform {0.000 10.000} -name CLK0 CLK0
create_generated_clock -source {pll_instance|altpll_component|pll|inclk[0]} -divide_by 3 -multiply_by 4 -duty_cycle 50.00 -name clk {pll_instance|altpll_component|pll|clk[0]}
create_generated_clock -source {pll_instance|altpll_component|pll|inclk[0]} -divide_by 3 -multiply_by 4 -duty_cycle 50.00 -name sdram_ctl_clk {pll_instance|altpll_component|pll|clk[1]}
create_generated_clock -source {pll_instance|altpll_component|pll|inclk[0]} -divide_by 3 -multiply_by 4 -phase -72.00 -duty_cycle 50.00 -name sdram_clk {pll_instance|altpll_component|pll|clk[2]}

